`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   20:18:26 04/14/2014
// Design Name:   Vigenere
// Module Name:   C:/Users/rpobrien/Documents/School/cis6930-network-security/SBoxCipher/Vigenere_tb.v
// Project Name:  SBoxCipher
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Vigenere
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module Vigenere_tb;

	// Inputs
	reg [127:0] key;
	reg [127:0] data_in;
	reg clk;

	// Outputs
	wire [127:0] data_out;

	// Instantiate the Unit Under Test (UUT)
	Vigenere uut (
		.key(key), 
		.data_in(data_in), 
		.data_out(data_out),
		.clk(clk)
	);

	initial begin
		// Initialize Inputs
		data_in = 0;
		key = "ZZZZZZZZZZZZZZZZ";
		clk = 0;

		// Wait 100 ns for global reset to finish
		#100;
		data_in = "AAAAAAAAAAAAAAAA";
		#50;
		$display("IN:\t%s", data_in);
		$display("OUT:\t%s", data_out);
		#100;
		data_in= "ABC EFG IJK MNOP";
		#50;
		$display("IN:\t%s", data_in);
		$display("OUT:\t%s", data_out);
		#100;
		data_in = "KLMNOPQRSTUVWXYZ";
		#50;
		$display("IN:\t%s", data_in);
		$display("OUT:\t%s", data_out);
		#100;
		data_in = "ZZZZZZZZZZZZZZZZ";
		#50;
		$display("IN:\t%s", data_in);
		$display("OUT:\t%s", data_out);
        
		// Add stimulus here

	end
	
	always #5 clk = ~clk;
      
endmodule

